1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having an ECL wired-OR circuit, constituted by a BiCMOS circuit.
2. Description of the Prior Art
An ECL circuit ("Emitter Coupled Logic" circuit) has a smaller logical amplitude, about 800 mV.about.1,600 mV, as compared with that of a CMOS circuit since in such ECL circuit a pair of bipolar transistors whose emitters are commonly connected operate as a differential amplifier. Due to the operation of small logical amplitude, a delay caused by wiring resistance and wiring capacitance is small, so that such ECL circuit is widely adopted in a semiconductor integrated circuit device which requires super high speed operation.
FIG. 8 shows a basic circuit of such ECL circuit. The ECL basic circuit shown in FIG. 8 comprises two stages. The first stage is a differential amplifier stage DA that is composed of a bipolar transistor Q10 which receives at its base an input signal from a terminal A, a bipolar transistor Q20 which receives at its base a reference voltage VR10 whose threshold level is set at a mid-point between a high level and a low level of the input signal, and a constant current circuit CS10 which is formed by a bipolar transistor Q30 and a resistor R30. The second stage is an emitter follower stage EF that is composed of bipolar transistors Q40 and Q50, which receive signals from load resistors R10 and R20 in the differential amplifier stage DA, and a constant current circuit CS20 which is formed by bipolar transistors Q60, Q70 and resistors R40, R50. One output terminal A' is connected to the emitter of the transistor Q40 and the other output terminal A' is connected to the emitter of the transistor Q50.
Signals which are in phase and in opposite phase with respect to the input signal are forwarded out from the output terminals A' and A', respectively, to the succeeding stage. The constant current circuit CS20 in the emitter follower stage EF operates to discharge the load capacitance connected parasitically to the output terminals A' and A' and to cause the output terminal A' or A' to change from its high potential to its low potential. The value of constant current which flows in the constant current circuit CS20 in the emitter-follower stage EF is generally in the range of about 0.2 mA.about.0.6 mA although it depends on the value of load capacitance.
FIG. 1 shows an example wherein the above described ECL circuit is embodied in a semiconductor memory and a decoder circuit outputs sixteen decoder signals on the basis of four address input signals. In FIG. 1, an address buffer a, which is composed of an ECL circuit, receives such as an address input signal X0 and outputs such as signals X0' and X0' of in phase and in opposite phase with respect to the input signal X0, respectively. The bipolar transistors Q3 and Q4 are of multi-emitter configuration. The bipolar transistor Q3 supplies the opposite phase signal X0' with respect to the input signal X0 to signal lines 1 and 2, and the bipolar transistor Q4 supplies the in-phase signal X0' with respect to the input signal X0 to signal lines 3 and 4. Likewise, also from another address buffer a, from which another address signal X1 is supplied, the signals X1' and X1' are outputted by two lines for each. The in-phase signals X1' is supplied to the signal lines 1 and 3, and the opposite phase signal X1' is supplied to the signal lines 2 and 4. The relation between the potentials of such signal lines 1.about.4 and the address signals X0 and X1 is explained below.
Consideration is made for the case where both the address input signals X0 and X1 are of ECL level low potentials (usually, when the maximum potential is to be Vcc=0 V, a high potential and a low potential of the input signal are assumed to be respectively -1.6 V and -2.4 V, and a reference voltage VR1 is assumed to be -2.0 V). As to the signal lines 1.about.4, as shown in FIG. 1, the emitter follower outputs of two paired signals each of the paired signals X0', X0' and X1', X1' are wired-OR connected. The signal X0' and X1' are of low potential and the signal X0' and X1' are of high potential. Consequently, only the signal line 3, to which the signals X0' and X1' are connected, is of low potential, and since at least one of the address buffer output signals X0', X0', X1' and X1' is of high potential, the other signal lines (1, 2 and 4) become high potential. That is, a selected signal line becomes low potential. In FIG. 1, the same is true in the relation between the input address signals X2, X3 and the signal lines 5.about.8, so that the selected one line among the signal lines 5.about.8 becomes low potential.
Next, the theory that one gate is selected by such signal lines 1.about.8 among the sixteen ECL gates b is explained. In the 2-input ECL gate b, an output becomes a logical NOR output. In FIG. 1, the bipolar transistor Q5 of the ECL gate b is connected with one line among the four signal lines 1.about.4, and the bipolar transistor Q6 is connected with one line among the four signal lines 5.about.8. The sixteen ECL gates b each having a first input terminal and a second input terminal are divided into four groups of the ECL gate groups b-1.about.b-4. For instance, to each of the first input terminals of the four 2-input ECL gates b in the ECL gate group b-1, the signals of the signal lines each selected from among the signal lines 1.about.4 in accordance with the address input signals X0 and X1, are inputted, respectively. And, to each of the second input terminals of the above four 2-input ECL gates b, the signal on the signal line 5 which is selected from among the signal lines 5.about.8 on the basis of the input signals X2 and X3 is commonly inputted. Likewise, the signal lines 1.about.4 are respectively connected to each of the first input terminals of the four ECL gates b included in the respective ECL gate groups b-2.about.b-4. The signal line 6 is commonly connected to the second input terminals of the four 2-input ECL gates b in the gate group b-2, the signal line 7 is commonly connected to the second input terminals of the four 2-input ECL gates b in the gate group b-3, and the signal line 8 is commonly connected to the second input terminals of the four 2-input ECL gates b in the gate group b-4. As described above, among the signal lines 1.about.4 only one signal line becomes low potential and among the signal line 5.about.8 only one signal line becomes low potential, and all the other remaining signal lines become high potential. As a result, by the signal lines 5.about.8, one gate group is selected from among the ECL gates groups b-1.about.b-4. For instance, when the signal line 5 is selected and is of low potential while other signal lines 6.about.8 are of high potential, all the ECL gates b other than those included in the ECL gate group b-1 output low potential. Since the signal line 5 is of low potential and is commonly connected to the four ECL gates b included in the gate group b-1, each of the output potentials of these four ECL gates b is decided by the potentials of the signal lines 1.about.4. Now, for instance, when the signal line 1 is selected and becomes low potential since X0 is high potential and X1 is low potential, only the terminal 11 among the output terminals of the ECL gates b becomes high potential and other output terminals 21, 31 and 41 become low potential. In this way. only one ECL gate is selected from among the sixteen ECL gates in accordance with a combination of the levels of the address input signals X0, X1, X2 and X3.
The foregoing has explained as to how the particular one ECL gate is selected by means of the wired-OR connection of the emitter follower outputs. Now, power consumption that comes a problem when the ECL gates are used is explained. In the CMOS and BiCMOS gates, a direct current does not flow under the steady-state output, so that no power is consumed therein. Therefore, in the case where the CMOS gates or the BiCMOS gates are used for a decoder circuit, the power consumption thereby is not necessary to be taken into consideration under the steady state. However, in the case of the ECL gate, a certain power on a constant current is consumed constantly irrespective of the output state of the ECL gate because the output is taken out by having the divided current of the constant current source flow into a pair of bipolar transistors (right and left in the drawings) forming the differential amplifier. Such consumption of current is very large when a decoder is constituted by the ECL gates. In the conventional decoder circuit shown in FIG. 1, for example, one of the ECL gates b alone consumes usually 0.5 mA of the constant current (the constant current circuit being composed of a bipolar transistor Q9 and a resistor R4). Since the number of the ECL gates b are sixteen, the decoder circuit in the part concerned consumes 0.5 mA.times.16=8 mA. In the actual 16K bit ECL RAM, the memory cell array is arranged, for instance, in a matrix form of 128.times.128, hence 256 ECL gates. Therefore, the consumption of power reaches even half the power consumption of the entire 16K bit ECL RAM and this has been a great problem to a high integration density of the semiconductor devices.
The decoder circuit using the conventional ECL gates as explained above involves large current consumption since a constant current continues to flow there regardless of the potential in the output terminal, that is, whether it is in a select state or a non-select state. Such a characteristic of the circuit has been one of the causes hindering a high density of integration of the semiconductor devices.